Flash memory cells are conventionally floating gate devices such as floating gate transistors formed on a semiconductor substrate. These memory cells are typically formed using self-aligned implants for the drain and the source. To create a memory cell, a gate stack is typically provided. The gate stack conventionally includes at least floating gate and a control gate disposed above the floating gate. The drain and the source are then formed by implanting the appropriate dopants around the gate stack. Thus, the gate stack is used as a mask to ensure that the source and drain are separated.
Currently, the length of flash memory cells are limited in part by the drain to source breakdown. At short channel lengths or high drain voltages, source to drain breakdown can occur. This breakdown causes the depletion of the source region to meet the depletion of the drain region, electrically coupling the drain and the source and preventing the memory cell from functioning correctly.
In order to reduce the drain to source breakdown, some conventional systems use a side implant, such as a drain side implant. These side implants are typically performed drain. Thus, these side implants increase the resistance of the memory cell to source to drain breakdown. For example, for a p channel memory cell, the dopant used is a p dopant, such as boron. The boron is implanted so that it is in the channel, typically next to the drain and should not be present at the source.
Because the implant is of a different type than the source, the implant should end before reaching the source. This is because the erase time is a function of the overlap between the gate and the source. If the side implant, which is of a different dopant type from the source, reaches the source, the time taken to erase the memory cell increases. Thus, the side implant should not overlap with the source.
In order to provide drain side implants in a conventional memory cell, the side implants are performed after the drain and source have been formed. To place these implants in the channel between the drain and source, and under the gate, large angle implants are used. For example, implants having a direction of approximately thirty to forty five degrees from normal to the surface of the semiconductor are used.
Although high angle implants can be used to provide a side implant, there are several disadvantages of high angle implants. Conventional implanters operate at angle on the order of six to seven degrees from normal to the semiconductor surface. In order to provide an implant at significantly higher angles, the manufacturing facility will have to change the implant angle drastically, which is difficult to do. In addition, high angle implants are difficult to tailor to specific structures. Finally, the reach of the high angle implant under the gate is somewhat limited.
Accordingly, what is needed is a system and method for providing a flash memory cell having increased resistance to breakdown without the drawbacks of conventional high angle implants. The present invention addresses such a need.